The following are the steps in the current bump process:
(1) Barrier/seed layer sputtering;
(2) Dry film resist (DFR) patterning: DFR lamination, exposure, then PET peel off and development;
(3) Pre-plating treatment: chemical dry etch (CDE) then a deionized water (DI) rinse;
(4) Plating;
(5) DRF removal;
(6) Under bump metal (UBM) etching; and
(7) Flux coating and reflow.
U.S. Pat. No. 6,181,569 B1 to Chakravorty describes a semiconductor chip package fabricated by bump processes using dry films. The wafer is sawed to separate the individual chips to yield semiconductor packages which have the same lateral dimensions as the chips.
U.S. Pat. No. 6,117,299 to Rinne et al describes a method of electroplating solder bumps of uniform height on integrated circuit substrates.
U.S. Pat. No. 5,028,983 to Bickford et al. describes electronic device packaging structures useful for electrically interconnecting an electronic device to a substrate.
U.S. Pat. No. 5,891,795 to Arledge et al. describes a method of creating high density interlayer interconnects on circuit carrying substrates employing a bump process using a dry film and curing process.